1. Field of the Invention
The present invention relates to a method of fabricating a gate electrode of a semiconductor device and, more particularly, to a method of making a nanoscale gate channel by forming reverse spacers and creating shallow junction structures by forming an elevated source/drain using a silicon epitaxial layer.
2. Background of the Related Art
The size of a metal-oxide-metal (hereinafter referred to as “MOS”) transistor has been gradually reduced as semiconductor devices become highly integrated. The width of a gate electrode and the area of a source/drain region are shrunken in proportion to decreasing size of the MOS transistor and, therefore, the contact resistance of the source/drain region as well as the resistance of the gate electrode are increased. Moreover, the source/drain region in a MOS transistor of a high-integrated semiconductor device has to be formed so that it has a shallow junction to avoid short channel effect. However, if the junction of the source/drain region becomes shallow in depth, the junction leakage current characteristics deteriorates and, therefore, the resistance of the source/drain region increases. In recent years, a method of reducing the contact resistance of metal interconnect lines by bringing a material layer such as a SiGe layer, which has a lower band gap energy than that of silicon, into contact with a metal interconnect line has been presented (Materials Research Society, pp. 223˜228, Shigeaki Zaima et al., 1997.).
On the other hand, it is generally known that a transistor fabrication method uses a salicide process to reduce the resistance of gate electrodes and the contact resistance of source/drain regions. However, in making a small-size MOS transistor of a high-integrated semiconductor device, the salicide process may deteriorate more seriously the junction leakage current characteristics of the source/drain region. To avoid this problem, a method using an elevated source/drain technology together with the salicide technology has been presented to reduce the resistance of gate electrodes and source/drain regions at the same time for the purpose of improving the junction leakage current characteristics. Here, the elevated source/drain technology forms a SiGe layer on the source/drain region using a selective epitaxial growth (hereinafter referred to as “SEG”) process.
For example, U.S. Pat. No. 6,537,885, Kang et al., describes a method of manufacturing a transistor having a shallow junction formation. Kang et al. uses two layers of a silicon epitaxial layer to fabricate a transistor having a good short channel effect and good drive current.
FIG. 1 is a cross-sectional view illustrating a transistor with an elevated source/drain formed by a conventional fabrication method. As shown in FIG. 1, a gate insulation layer 3 such as a thermal oxide layer is formed on a predetermined area in a semiconductor substrate 1 with a first conduction-type. Then, a gate pattern 5 is formed on the gate insulation layer 3. The semiconductor substrate is made of single crystal silicon. The gate pattern is a doped polysilicon layer. In another embodiment, the gate pattern may consist of a doped polysilicon layer and a capping layer. The capping layer is a silicon nitride layer or silicon oxide layer. Next, spacers 9 made of an insulating material such as silicon oxide or silicon nitride are formed on the sidewalls of the gate pattern. A source/drain region 13 with a second conduction-type is then formed on the surface of the substrate at both sides of a channel area under the gate pattern. The source/drain region is a lightly doped drain (hereinafter referred to as “LDD) type. The second conduction-type is opposite to the first conduction-type. Then, a SiGe layer 15 doped with impurities is selectively formed on the source/drain region. Here, the SiGe layer 15 has the same conduction-type as the source/drain region. A metal silicide layer 17a is then formed on the SiGe layer. Here, if the gate pattern is a doped polysilicon layer, the SiGe layer and the metal silicide layer are also formed on the gate pattern in sequence. As a result, an elevated source/drain consisting of the source/drain region and the SiGe layer are completed, as shown in FIG. 1. Here, the metal silicide layer is a layer consisting of silicon and a fireproof metal such as cobalt, tantalum, or titanium. The metal silicide layer has lower specific resistance than that of the source/drain region 13 doped with impurities. In addition, the SiGe layer positioned between the metal silicide layer and the source/drain region has a lower band gap energy than that of the silicon substrate.
By adopting the elevated source/drain structure, the above-described prior art can increase the distance between the metal silicide layer and the junction area of the source/drain region in a MOS transistor while the low junction depth of the source/drain region is maintained. Accordingly, the leakage current characteristics of the source/drain region as well as the short channel effect of the MOS transistor can be improved. However, the described prior art includes the epitaxial layer made of a different material from the silicon substrate, which has to be selectively deposited over a source/drain region. Moreover, the epitaxial layer has additionally to be doped with the same impurities as those doped into the source/drain region. Therefore, the process for fabricating a transistor becomes complicated.